`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:05:50 03/30/2014 
// Design Name: 
// Module Name:    change_sound 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module One(speaker, clk);  
  
	input clk;    
	output speaker;      
	reg [27:0] tone;   
	reg [14:0] counter;  
	reg speaker; 
		
	wire [6:0] fastsweep = (tone[22] ? tone[21:15] : ~tone[21:15]);    
	wire [6:0] slowsweep = (tone[25] ? tone[24:18] : ~tone[24:18]);    
	wire [14:0] clkdivider = {2'b01, (tone[27] ? slowsweep : fastsweep), 6'b000000};    
		
	always @(posedge clk) tone <= tone+28'b1; 

	always @(posedge clk) 
		if(counter==0) counter <= clkdivider; 
		else counter <= counter-15'b1;       
		
	always @(posedge clk) 
		if(counter==0) speaker <= ~speaker;    
   
endmodule
